Analysis and Modeling of the Charge Collection Mechanism in 28-nm FD-SOI

TCAD simulations on 28-nm fully depleted silicon on insulator structures are used to analyze the charge collection mechanism leading to parasitic current when an ionizing particle passes through the devices. A description of the components constituting the parasitic current is carried out for several strike locations. The bipolar effect does not arise as the main cause of the parasitic current as usually reported. The impact of the drain-source polarization in the collection mechanism is highlighted. A compact model was made, and a quantitative effect was simulated for the pass-gates in an SRAM cell using a variation of the bitline supply.