An architecture for energy-efficient hybrid full adder and its CMOS implementation

In this paper an energy-efficient hybrid 1-bit full adder design is reported. The main aim of our work is to achieve low power and high speed design goals. The proposed hybrid adder is used the combination of CMOS logic (Complementary Metal Oxide Semiconductor) and transmission gate (TG) logic. The circuit has been implemented using Tanner EDA tools in 90 nm technology. Performance parameters such as power and delay have been compared with the existing designs such as complementary pass-transistor logic based adder, transmission gate logic based adder, transmission function adder, hybrid adders, and so on. Power consumption of the proposed adder is found to be 0.1292 μw at 90 nm for 1.2 V supply and delay in the signal propagation is measured as 0.0247 ns for 90 nm technology. It means that proposed adder consuming extremely low power and low propagation delay than existing designs for the same testing environment. Power Delay Product (PDP) is considered as product of power and delay values signifies energy requirement of the design.