Radiation-Hardened Flip-Flops With Low-Delay Overhead Using pMOS Pass-Transistors to Suppress SET Pulses in a 65-nm FDSOI Process

In this paper, we propose radiation-hardened flip-flops (FFs) based on the adaptive coupling FF with low dynamic power and short delay overhead in a 65-nm fully depleted silicon on insulator process. We designed four FFs composed of a master latch with pMOS pass-transistors to reduce a delay time overhead and a slave latch with stacked transistors for high soft-error tolerance. We evaluated the radiation hardness of the newly designed FFs using TCAD simulations, α particle test, and neutron irradiation test. TCAD simulations show that the proposed structure has enough radiation hardness against secondary particles generated by neutrons. The α irradiation results show that error probabilities of the proposed FFs are 1/400-1/130 smaller than conventional radiation-hardened stacked FF. Neutron irradiation results show that soft-error rates of the proposed FFs are 1/16-1/7 lower than stacked FF. No significant differences in soft-error tolerance were observed in any of the proposed FFs under all static conditions. The experimental results suggest that the pMOS pass-transistors can effectively suppress soft errors in terrestrial regions with a low-delay overhead.