A Low-Noise $RC$ -Based Phase Interpolator in 16-nm CMOS

This brief describes a passive analog phase interpolator, utilizing a switched RC-network. The proposed circuit eliminates the current sources in a phase interpolator based on constant-slope charging. By eliminating the current source, the noise is significantly reduced due to the reduction in thermal and flicker noise. The phase interpolator has a resolution of 6 bits and is implemented in a 16-nm CMOS process. The maximum differential non-linearity is measured to be 0.1 LSBs at a 192-ps input time delta. The circuit draws 0.2 mW from a 0.8-V supply, and occupies 0.004 mm
²
.