Output impedance design of distributed domains with high frequency voltage regulators

This paper presents analysis & methodology for impedance design of distributed voltage domains supplied from high frequency voltage regulators (VRs). The approach addresses entire system including the combination of routing parasitics, decoupling capacitor dynamics, and control design for a low impedance solution. The detailed modeling is applicable to any power converter — on die, on package, power management IC (PMIC) & mother board VRs, where control bandwidth, decoupling capacitor & power delivery network (PDN) resonances, and load transients are in a narrow frequency range.