Performance Analysis and Enhancement of Negative Capacitance Logic Devices Based on Internally Resistive Ferroelectrics

In this letter, we present a comprehensive performance analysis of ferroelectric (FE)-based logic gates and repeaters. In addition, we highlight the key aspects of negative capacitance FET (NCFET) characteristics, including the proper circuit initialization, the negative capacitance (NC) effect on leakage currents, and the impacts of the FE viscosity coefficient. The threshold voltage adjustment is proposed to optimize the NCFET-based devices according to the activity factor. Furthermore, we study the interconnect repeater insertions and optimize the numbers and sizes of repeaters to minimize the overall energy-delay product. The NCFET is implemented in SPICE, with FE dynamics described by the Landau-Khalatnikov equation. Our analyses with the SPICE circuit model can provide useful insights into future studies of low-power devices.