A low power two-step cyclic time-to-digital converter without startup time error in 180 nm CMOS

We present a low power, small area time-to-digital converter (TDC) based on Venier cyclic digital controlled oscillator (DCO) structure. The TDC is designed to be combined with an array of single photon avalanche diodes (SPAD) arranged in a digital silicon photomultiplier (SiPM) architecture to form a fluorescence lifetime sensor. The high dynamic range is achieved by using two individual counters in two (coarse and fine) conversion steps. The TDC is fabricated in 0.18 μm CMOS process in a compact chip area of 0.23 × 0.12 mm
²
. Using a 1.8 V supply, the TDC achieves a resolution of 100 ps, dynamic range of 160 ns and an average power consumption of 0.8 mW.