Pentavariate $V_{\mathrm{min}}$ Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read

Subthreshold and near-threshold operations are viable approaches towards reducing both static and dynamic power in Static Random Access Memory (SRAM). However, supply scaling in SRAM cells is severely limited by process variations. Additionally, cell performance is greatly affected by local mismatch in subthreshold region, thereby prohibiting low voltage operation. In order to mitigate these issues, we present a ten-transistor (10T) SRAM cell with capability of performing a variation tolerant write operation in deep subthreshold region without the implementation of additional peripheral circuitry or assist technique. The unique topology of the proposed cell also aids in reducing the bit line offset voltage, thereby improving read access performance. In addition to read and write performance, the hold stability has also been improved, resulting in significant Vmin gains. The Vmin of all cells has been evaluated at the 6σ failure point (P
_Fail
= 10
^-9
) using a comprehensive pentavariate probability anaylsis, considering both static and dynamic measures. At respective Vmin, the proposed 10T cell consumes up to 39× and 6.6× lower hold power than the conventional 6T and 8T cells, making it a viable candidate for portable electronics or low power sensors.