A 1-GS/s 11-Bit SAR-Assisted Pipeline ADC With 59-dB SNDR in 65-nm CMOS

We present an 11-bit 1-GS/s time-interleaved (
$\times 2$
) successive approximation register (SAR)-assisted pipeline analog-to-digital converter (ADC) for wideband direct sampling radio-frequency receivers. The proposed ADC architecture combines the speed advantage of the pipeline algorithm and the structural simplicity of the SAR structure. Consequently, both the structure and the operation of the pipeline stages are simplified, thereby enhancing the conversion rate and accuracy. In particular, the proposed ADC eliminates the multiplying digital-to-analog converter in the conventional pipeline ADC, hence compatible with process portability. The prototype ADC fabricated in 65-nm CMOS process achieves SNDR ≥ 56-dB across 500-MHz Nyquist bandwidth at 1GS/s conversion rate with 230-mW power dissipation. When benchmarked against state-of-the-art pipeline ADCs, it features a competitive figure-of-merit, i.e., 449.2 fJ/conv.-step.