A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOS

Improving the energy efficiency of wireline interconnects has become a necessity to sustain growing data rates. Low-voltage wireline link operation is a promising approach to achieve close to pico-joules/bit energy efficiency [1-3]. However, conventional low-voltage wireline links suffer from two limitations: (a) limited equalization (12dB) or no channel equalization, and (b) low data rates (8Gb/s @0.75V) even with fine process technology nodes [2]. Limited equalization in low-voltage links is due to the fact that conventional equalization (FFE, DFE) is performed on the high-speed data path. As a result, when the supply voltage is reduced (below 0.6V), the bandwidth of the data path is severely diminished, which compromises FFE and DFE operation. Moreover, the requirement to generate and transport narrow clock pulses in conventional low-voltage output drivers limits the maximum achievable data rates [1,3]. In view of these limitations, we propose a new approach to equalize heavy channel loss at low supply voltages by moving the equalizing operation out of the data path and into the clock path. Integrated pulse width modulation (iPWM) has been demonstrated to efficiently equalize heavy channel loss by encoding data transition edges [4]. In this work, we present a modified iPWM encoding, an energy-efficient wireline transceiver with a clock-domain low-voltage iPWM encoder, and a low-voltage multiplexer + output driver architecture, which can operate from 0.5-to-0.9V and 3-to-16Gb/s compensating 27dB channel loss at 10Gb/s with an energy efficiency of 1.8pJ/b. Compared to prior low-voltage links [2], the proposed transceiver can compensate 15dB higher loss at 25% higher data rate (10Gb/s) operating at 13% lower supply voltage (0.65V) while using an older technology node (65nm). Compared to state-of-the-art iPWM-based wireline transceiver operating at nominal supply voltage [4], the proposed transceiver achieves 2.5x lower energy/bit while compensating similar channel loss, and compared to a conventional equalization-based transceiver it compensates 8dB higher loss with similar energy efficiency [5].