Design margin elimination through robust timing error detection at ultra-low voltage

This paper discusses a timing error masking-aware ARM Cortex M0 microcontroller system. Through in-path timing error detection, operation at the point-of-first-failure is possible without corrupting the pipeline state, effectively eliminating traditional timing margins. Error events are flagged and gathered to allow dynamic voltage scaling. The error-aware microcontroller was implemented in a 40nm CMOS process and realizes ultra-low voltage operation down to 0.29V at 5MHz consuming 12.90pJ/cycle, or a MEP of 11.11pJ/cycle at 7.5MHz. Measurements show the in situ approach is ideal to overcome traditional SS corner design margins (75% energy reduction). Additionally it overcomes the limitations introduced by replica path based techniques typically plagued by intradie variations (8% reduction).