Robust event trigger generation for post silicon validation

It is extremely difficult to eliminate all the design flaws that may exist in a complex integrated circuit design before fabrication due to limitations of pre-silicon verification methodology. Post-silicon validation has become pivotal in order to fix these design flaws which could not be identified during pre-silicon verification. One of the most effective silicon debug techniques is tracing internal signals during circuit's normal operation and using the gathered information to identify and fix the root cause of the problem. Trace-based technique involves logic analysis that works on the principle of event triggering. Existing trigger generation methods suffer from the false multi-triggering problem due to dependency on exact value of delay provided by internal delay elements and do not give a stable performance against PVT variations. This paper demonstrates a robust technique for generating these triggers which is independent of exact value of delay provided by internal delay elements and immune to false multi-triggering along with a consistent behavior across the PVT variations.