A Fast Technique to Reduce Power Consumption on Linear Block Codes Used to Protect Registers

In recent years, both radiation induced faults and power consumption have become important factors to consider when designing circuits for space applications. These faults can affect registers by corrupting the information stored in them. In order to prevent this, redundancy is added to the register, usually in the form of extra parity bits. However, the addition of these bits results in an increase of power consumption due to the operations needed to calculate, store, and check their values. In this paper, we present a technique that reduces the power consumption introduced by linear block codes when they are applied to registers. This technique can be applied in a fast way and with low computational cost and is intended for registers in which the switching activity amongst their input bits presents high heterogeneity.