Performance optimization in flip flop circuit design

In delay flip flop the storing of data get restricted due to leakage current which can limit flip flop from performing its operation. The 5T proposed delay flip flop using modified SVL design had several advantages in comparison with the conventional D FF in terms of reduced transistors count, decreased leakage current, increases stability and high speed. In this paper flip flop topologies using Cadence Virtuoso Tool at 45nm technology is proposed.