Comprehensive Operation Chaining Based Schedule Delay Estimation During High Level Synthesis

Design space exploration (DSE) during high level synthesis (HLS) involves a major step called scheduling which is responsible for estimating the delay of a control data flow graph (CDFG). However, a DSE process which concurrently estimates schedule delay by considering functional unit (FU), switching devices (such as mux, demux) and storage elements (such as latches), much before creation of its controller timing sequence, is an unsolved problem in the literature. Current DSE approaches either consider only FU during scheduling, or generate the complete controller timing sequence for delay evaluation of a CDFG based on provided resource constraint. The prior case, though fast but is not realistic in delay estimation. The latter case, though very slow, but provides realistic delay estimation. This paper solves the aforesaid problem by proposing a balanced DSE methodology that includes comprehensive delay estimation by considering combined delay of FU, switching devices and storage elements directly from scheduling. Results indicate improvement in achieving more realistic delay estimation process than previous approaches.