Energy Efficient NoC Router for High Throughput Applications in Many-Core GPUs

With the development of many-core GPU clusters, researchers are forced to deal with an increased power consumption and a shortage of chip area. Numerous efforts have gone into creating a scalable and a power and area efficient Network-on-Chip solution. However most of these solutions either compromise on performance or are not scalable. In this work, we propose a scalable, minimally buffered router to minimize chip area and use the concept of Marching Memory to save power without having to compromise on the network performance. We achieve an average latency reduction of 27.9% and an average throughput increase of 30.46% as compared to conventional minimally buffered architectures.