Impact of Local-Interconnect to Gate Overlay on Series Resistance Compensation for Injection Velocity Extraction

The extraction of the injection velocity in CMOS requires compensation of the transistor series resistances. They are usually evaluated in the linear regime, assuming that the source and drain terminals contribute equally to it. Due to the overlay between gate and local interconnect, this is however not the case. This paper investigates the consequences on the injection velocity extraction procedure, and proposes a new approach to compensate for the asymmetry of the device. The difference between the saturation transconductances obtained by swapping the MOSFET junction terminals is used to extract the source resistance, and thus enables accurate resistance compensation of the inversion charge and current in the saturation regime. This method is tested on a bulk FinFET technology to demonstrate its validity, and the results are correlated with metrology measurements.