Impact of si/sige heterojunction on dual gate and dual gate dielectric material SOI finfet

Considerable amount of leakage effects in the planar transistors halted the pace of technology scaling, these effects can be reduced with the non-planar transistors. Two configurations of Fin shaped Field Effect Transistors having dual materials for gate as well as for gate dielectric but diverse in terms of active fin region material have been analyzed for their contribution to leakage current. Design and simulation of both the structures having gate length of 14nm have been done using TCAD simulator. Effect of integrating two materials in the active fin region on performance parameters such as on and off current, on-off current ratio and subthreshold swing has been inferred. Leakage current of value 1.99×10
^-16
A has been obtained in heterojunction structure, which reveals its advantage over homojunction structure making them a considerable choice for low power dissipating integrated circuits.