Atomistic- to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnects

In this paper, we present a hierarchical model for doped single-walled carbon nanotube (SWCNT) for on-chip interconnect application. Our model aims to study CVD grown SWCNTs while considering defects and contacts to metal electrodes. Both defects and poor contacts can worsen CNT conductivities and ultimately deteriorate their interconnect performance. We investigate the fundamental physical mechanism of charge-based doping with the purpose of improving SWCNT electrical conductivity as well as a potential solution to alleviating the impact of defects and contact resistances. We present an atomistic model to study the number of conducting channels of doped SWCNT with different vacancy defect configurations. Circuit-level electrical modeling and simulations are performed on SWCNT interconnect while considering the impact of doping, defects, and contact resistance. Simulation results show up to 80% resistance reduction by doping, where 17% of delay increases due to defects. Additionally, we observe doping can mitigate the impact of defects by more than 12%, but there is almost no improvement in the contact resistance.