Remotely configurable fault-tolerant FPGA-based pacemaker

The Pacemaker is the most famous Implantable Medical Devices which is used in treating bradycardia and tachycardia. The pulse generator is the brain of the pacemaker; accordingly, it should be implemented using a powerful flexible platform. In this paper, an FPGA-based pulse generator is implemented. The Dynamic Partial Reconfiguration (DPR) property of FPGAs is used to allow the remote change of the operational mode of the pacemaker. A pacemaker is a real time critical system; therefore, it must be very reliable. Accordingly, Fault-Tolerant techniques should be applied to the FPGA-based pulse generator. Two Fault-Tolerant techniques are under investigation: two Duplication With comparison (DWC) circuits and Sift-out. The fault model used is Single Event Upsets (SEUs). Remote recovery takes place using DPR. Markov Models are used for reliability calculations. Results show that the Sift-Out technique is more reliable than the two DWC one.