0.23-V Sample-Boost-Latch-Based Offset Tolerant Sense Amplifier

An offset tolerant SRAM sense amplifier (SA) deployed with sample-boost-latch technique to facilitate both common mode and differential mode boosting is proposed. The common mode boosting enables proposed SA, SBLSA to operate deeper into the subthreshold regime whereas the differential mode boosting helps tolerate undesirable mismatch conditions by driving cross-coupled inverters with boosted differential voltages. The proposed boosting circuit first samples the bitline voltages and then isolates the sampled voltages from the highly capacitive bitlines followed by the boosting phase on relatively much less internal input capacitances of the latch. Arrays of SBLSA and conventional voltage latch SA (VLSA) were fabricated in 65-nm-GP CMOS (512 each). At 25 °C, SBLSA achieves 23.3% reduction in directly measured standard deviation of input-referred offset (across 16 ICs, 8192 SAs) and 38.5% improvement (typical IC) in sensing delay at 0.3 V. SBLSA offers reliable operation across entire temperature range of -25 °C to 85 °C at 0.35 V whereas it is 0.41 V for VLSA. Finally, SBLSA operates reliably at the minimum supply of 0.23 V at 25 °C which is 30 mV less compared to VLSA.