FPGA based hardware implementation of fault detection for microgrid applications

This paper describes hardware implementation for fault detection on a power grid using FPGA. The fault detector implements a Haar wavelet algorithm to detect the fault, the fault is indicated by a change of phase angle and amplitude on sinusoidal wave. Sinusoidal wave on the grid must be sampled into a digital value using an analog to digital converter (ADC), then the ADC's value transferred into a wavelet block in the FPGA. The wavelet block in FPGA will calculate the data measured by ADC using Haar wavelet algorithm, and detect the fault by change in the ADC's sampling value. The calculation of Haar wavelet implements a systolic array processor, and the data fault simulation will be generated by a modelling software.