Fabrication and simulation of vertical Ge-based P-channel planar-doped barrier FETs with 40 nm channel length

Ge integrated on Si is a promising candidate for energy-efficient field effect transistor (FET) applications due to its high mobility and compatibility to CMOS technology. Nevertheless, using Ge in FET fabrication is challenging due to difficulties in controlling the transistor channel/gate oxide interface properties and suppressing crystal defects such as threading dislocations that arise from Ge integration on Si. Furthermore, the smaller bandgap of Ge compared to Si can give rise to higher band-to-band tunneling leakage currents [1-2]. All these challenges severely affect the on-state (I
_on
) and off-state (I
_off
) currents. With respect to simulation, the majority of the physical models parameters are calibrated for Si. For Ge, the parameters are still less well known. In this work, we present the fabrication and characterization of vertical Ge-based p-channel Planar-Doped Barrier FETs (p-PDBFETs). Our experimental results are then used to calibrate our simulation model. Based on simulation data, an improved transistor design is proposed.