Cu/poly-Si damascene gate structured MOSFET with Ta and TaN stacked barrier

A Cu/Si layered-gate-structured MOSFET with Ta and TaN stacked barrier layers fabricated using a Cu damascene process has been developed for high-performance and reliable Si ULSI devices. A sheet resistance of 0.5 ohm/sq. was achieved with a 0.25 /spl mu/m gate length. The Ta and TaN layers guarantee reliable gate oxide (7.5 nm) after 500/spl deg/C thermal processing in nitrogen with forming gas annealing.