Design of programmable parallel LDPC decoder

A partial parallel architecture for LDPC (Low Density Parity Check Code) decoder is proposed. The overall architecture is based on MIMD (Multiple Instruction Stream Multiple Data Stream), the internal calculation unit is based on SIMD (single instruction Stream multiple data Stream). The processor uses the programmable method to realize the NMS (normalized minimum sum) decoding algorithm, can get a higher speed of calculation and easier chip layout. The architecture of the processor has passed the timing simulation on XILINX Kintex-7, the maximum clock frequency is 175MHz. Experimental results show that the structure is suitable for multi code long and multi bit rate LDPC decoder.