Test and validation of electronic systems

Computers are growing in complexity at an ever increasing rate. The ability to properly validate all of the processor's functions is a problem faced by processor manufacturers. A major area for improvement in reducing acquisition time is eliminating the wait for physical prototypes prior to commencement of software test and debug. It is not unusual for this waiting period to account for as much as one-third of the development cycle. Thus the current interest in hardware/software co-design. By overlapping phases of development, co-design brings the test and validation of a system closer to the architectural phase where it is needed most. Early verification that a design meets the customer's requirements minimizes the risk of building a system no one wants. CPU Technology's Behavioral Verification Technology/sup TM/ (BVT) and SystemLab/sup TM/ provide a means to thoroughly validate complex processors. BVT was invented to address the validation interests of all of the participants in the computer industry. It enables the rapid development of formal instruction-set architecture validation suites for any computer. SystemLab expands beyond hardware/software co-design to the virtual laboratory that consists of virtual prototypes made from software models rather than hardware components.