A low complexity EPR-IV equalizer for hard disk read channels

This work proposes an EPR-IV equalizer for HD read channels. The design has been optimized at architectural level, in order to single out a low complexity solution. In the circuit design such low complexity can be translated into low power and area consumption, which are characteristics typically required in modern HD systems. The proposed architecture is based on fractionally spaced equalization that can highly reduce the complexity associated with timing recovery. Furthermore a sampled data approach leads to improved equalization performance, allowing to reduce the ADC accuracy and to remove any digital post-processing. System and transistor level simulations prove that the proposed solution provides the required equalization to the read signal and that the circuit can be implemented in a standard CMOS 0.35 /spl mu/m technology.