Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC

This work addresses the new problem of timing variation-aware (TV) task scheduling and binding (TSB) for multiprocessor system-on-chip (MPSoC) architecture in the system-level design, where tasks have the full flexibilities of resource (i.e. processor) sharing to meet the design constraints. With the timing variation of processors’ clock speed, it has been observed that the consideration of the effect of resource sharing on the resulting performance yield computation is critically important for accurate design space exploration and evaluation in the system-level design. Nevertheless, unfortunately the previous statistical static timing analysis (SSTA) in the system level has never considered the resource sharing in the performance yield computation, or has overly simplified it by employing the gate-level SSTAs. In this work, we overcome this limitation of the previous work. Specifically, under the data of clock speed variation of each processor, we propose an effective technique of SSTA, called TSB-SSTA, on TSB in the presence of resource sharing and develop a TV framework, called TSB-TV, of TSB that tightly integrates TSB-SSTA. Through experimentation with the benchmark designs, we have tested the effectiveness of our approach. In summary, compared with the results by the conventional TV TSB, TSB-TV enhances the performance yield of designs by 30% on average.