Accurately Simulating the Effects of Faults in VHDL Models Described at the Implementation-Level

Simulation-based fault injection (SBFI) is an indispensable technique for the early verification and dependability assessment of target circuits along the semi-custom design flow. Most precise results can be obtained by models described at the implementation level, as they accurately reflect the functional/timing behavior and the structure of the resulting circuit. These models consist of a list of connections between technology-specific components (netlist), annotated with actual post-place-and-route delays. The simulation models of these components (macro-cells) are distributed in vendor-specific libraries that, in the case of VHDL, are described in accordance with the VITAL standard. This standard establishes the procedures, types, and packages (primitives and timing) to be used to ease development and speed-up simulation. However, it also imposes a very complex structure and run-time peculiarities that should be taken into account to correctly reproduce the effects induced by simulated faults. This work defines how faults should be injected into components described following the VITAL standard to accurately simulate the effects of the most common fault models at the logic level (bit-flip, pulse, and stuck-at). An implementation-level model of the LEON3 processor, defined using the commercial and widely-used Xilinx's simprim library, demonstrates the importance of considering accurate faults injection procedures for the deployment of representative SBFI experiments at this description level.