Serial interface engine asic with usb physical transceiver based on fpga development board

The data transmission is fairly quick and easy in recent years. Nowadays, there are many serial data transmission methods, such as I2C, SPI, RS-232, USB (Universal Serial Bus), and so on. Recently, USB not only works with convenience but also transmits data fast. It becomes a standard peripheral interface between FPGA development board and personal computer (PC). To satisfy those requirements, the data transmission speed and data volume of USB physical transceiver are continuously improved. The transmitted data will be queued with first-in first-out register (FIFO), proceeding with serial interface engine (SIE), compiling with the USB packet format, and converting it into an analog differential signal by using the Cypress's USB PHY (Port Physical Layer) chip. Then the USB packet will be sent from the transmitted FPGA board to the received FPGA board through the USB cable. Two FPGA boards with USB PHY are used to verify the transceiver function. After the functional verification has been completed, an application-specific integrated circuit (ASIC) of FIFO and SIE are implemented with TSMC 0.18μm CMOS technology. The gate counts, power consumption, operating frequency, and chip area are 14,547, 2.6742 mW, 50 MHz, and 0.7×0.67 mm
²
, respectively, at the supply voltage of 1.8 V and the total pins of 40 pins.