A novel flip-flop circuit for sub-threshold application

This paper proposed a novel sub-threshold flip-flop circuit with ultra-low voltage and ultra-low power - Half Clocked Master-Slave Logic (HCMSL). This circuit is optimized from the C
²
MOS circuit and pseudo NMOS ratioed logic style and composed of pre-driving stage and output stage. Compared to conventional flip-flop circuits, it has comparative static power consumption and its output capacitance decreases a lot and the performance is also improved when it working in sub-threshold region. The circuit was simulated as well as the conventional flip-flop circuits in CMOS 130nm. In simulation it indicates 30%-70% less delay than conventional flip-flops and less power consumption when the logic activity exceeds 200 kHz.