Deadline, Energy and Buffer-Aware Task Mapping Optimization in NoC-Based SoCs Using Genetic Algorithms

In Systems-on-Chip (SoCs) based on Networks-on-Chip (NoCs), the timing requirements of target applications can be met by using virtual channels and traffic differentiation mechanisms to prioritize the most urgent communication streams. However, the use of virtual channels in NoCs results in silicon and power overheads as they are usually implemented by means of additional buffers and multiplexers. In this context, this paper presents an optimization flow to perform the mapping of applications on NoC-based SoCs, aiming to meet the time requirements and minimize the costs arising from the use of virtual channels. The optimization flow applies a multi-objective heuristic that minimizes the communication deadline miss ratio, the number of virtual channels per router and the static power consumption. The heuristic is based on the NSGA-II genetic algorithm and performs task mapping, priority assignment, and virtual channel configuration. The proposed mapping optimization is evaluated by measuring the inter-task communication latency using a cycle-accurate NoC simulator. The optimization flow is able to identify a series of mappings that represent trade-offs over the metrics of interest, reducing the deadline miss ratio and the costs associated with virtual channels.