A topology optimization method for low-power logic circuits with dual-threshold independent-gate FinFETs

This paper proposes a topology optimization method for dual-threshold (DT) independent-gate (IG) FinFET circuits. In the proposed method, a node extraction algorithm is developed to extract the characteristic nodes of a BDD expression, which are suitable to be realized with the compact logic gates based on the DT IG FinFET devices, and then the equivalent replacement program that these extracted characteristic parts are replaced with the compact logic gates is carried to obtain the final optimized circuit netlists. The MCNC benchmarks are used to verify the effectiveness of the proposed topology optimization method. All the circuits synthesized by the proposed method and the commercial synthesis tool (Design Compiler) are simulated using Hspice with FinFET BSIM model to fairly compare their circuit performances. The results show that the proposed method could greatly improve the performance of the circuits in terms of power dissipation and power delay product compared with the Design Compiler.