Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology

Logic gates for ultra-low voltages suffer from speed and robustness degradations, which are highly associated with the process technology. In this work a methodology for the automated design-space exploration of standard logic gates for a 28 nm FD-SOI technology is shown. Comprehensive design space explorations of inverter and nand2 gates show the benefits of back-biasing at sub-threshold supply voltages. A comparison of Pareto points with a common energy consumption of 1 fJ shows that for the inverter minimum variation of 3.66 % is achieved utilizing 4 stacking transistors (LVT type), while delay is increased by 21 %. For nand2 gates the standard CMOS implementations (LVT type) outperforms transmission gates and stacked transmission gates in terms of variation (3.84 %) and delay (2.99 ns).