A Nyquist-rate pipelined oversampling A/D converter

A pipelined /spl Delta/-/spl Sigma/ analog-to-digital-converter architecture is described that incorporates the high speed of pipelined converters and the high resolution of oversampling quantization. A prototype, containing both modulation and decimation circuits on a single chip, is implemented using a 1.2-/spl mu/m commercial CMOS process. It uses charge-coupled-device elements to perform pipelined analog operations. It exhibits a maximum data rate of 18 MHz, a signal-to-noise ratio of 74 dB, spurious-free dynamic range of 78 dB, differential nonlinearity of <0.15 LSB at 13 bits, and power dissipation of 324 mW.