Workflow for NoC/DSP multicores-based platform: From Matlab/Simulink models to hardware mapping and scheduling

Programming multi-cores based Digital Signal Processors (DSP) becomes increasingly complex. This complexity is related to the rapid evaluation of Telecommunication and multimedia systems accompanied by a rapid increase of user requirements in terms of latency, power computation, consumption, etc. Workflow showed to be a successful approach for programming the applications based on NoC-DSP platforms. The main goal of this work is the design of a hardware/software system in an automated manner. In this paper, we present our proposed workflow taking as entry point a Simulink file (.mdl or .slx) derived from embedded Matlab functions. This workflow allows an automatic transformation from a Simulink model to synchronous dataflow (SDF) model, followed by a mapping and scheduling steps in order to obtain the C code to be executed by each core within the designed platform. Our approach is based on the synchronous and hierarchical behavior of both Simulink and SDF, aiming to simplify the generation of a compatible c code for a Noc-DSP platform.