PAAS: A system level simulator for heterogeneous computing architectures

Heterogeneous computing with hardware accelerators is a promising direction to overcome the power and performance walls in traditional computing systems. CPU-accelerator integrated architectures, such as CPU with ASIC or FPGA based accelerators, are able to provide customized processing according to application requirements and are thus particularly attractive to speed up computation-intensive applications. Therefore, system level simulation showing the interaction among CPUs, hardware accelerators and memory system precisely is important for performing design space exploration leading to architecture and design optimization. In this work, we present PAAS (Processor Accelerator Architecture Simulator), a system level simulator to enable cycle-accurate full system simulation of CPU-accelerator heterogeneous systems. PAAS can easily support flexible architectural configurations, such as different on-chip interconnection topologies, memory hierarchy, etc. Using PAAS, this paper also presents the analysis of the impact of different architectural configurations on the performance of benchmark applications with different execution characteristics using FPGA based accelerators. Furthermore, as an example showing the research capability of PAAS, this paper proposes and investigates a cache-partitioning scheme for improving the performance of shared-cache based CPU-FPGA systems.