An architecture for two-dimensional discrete wavelet transformation of real-time video processing to optimise memory usage and reduce frame delay

In this paper, a memory optimizing architecture for FPGA implementation of a two-dimensional discrete wavelet transformation with the lifting scheme for real-time video by processing is proposed. At first, a discrete wavelet transformation (DWT) aiming for a Haar wavelet is implemented by the MATLAB/Simulink HDL coder with outputs the approximation, horizontal details, vertical details and diagonal details of the input frames. This implementation uses counters and FIFOs from the HDL coder library to acquire rows and columns of the input frame and sort the output of the DWT for the display. Furthermore, the FPGA hardware uses on-board RAM to display a sorted output to VGA in four sections on a screen with the resolution of 600 × 800 pixels. The algorithm addresses as the solution for problems related to low on-board memory and more than a frame delay during display. Later, the Simulink model is tested on the Altera Intel DE2i-150 board and applied to real-time video processing from a Terasic 5 MB digital camera at the rate of 15 frames per second.