Achieving performance speed-up in FPGA based 4:2 compressor using fast carry-chains

Compressors form the basic element of arithmetic circuits that are dominated by multi-operand addition operations. Compressor circuits based on carry-save logic have been used in past to realize parallel multipliers for ASIC implementation, however, owing to the peculiar architecture of FPGAs, these circuits do not map well on these platforms. In this paper, FPGA implementation of 4:2 compressor circuit is carried out. The compressor architecture considered in this paper involves rippling of carry. This property is exploited by using fast carry-chains to handle the rippling of carry. The use of carry-chain ensures that underlying resources are utilized efficiently. The proposed implementation is compared against traditional approach in terms of resources utilized, speed and power. Both combinational and pipelined implementations are considered. The results indicate that the proposed implementation shows substantial improvement in performance over the traditional approach.