VHDL placement directives for parametric IP blocks

Today's FPGAs are no longer used simply for glue logic. They possess sufficient gate capacity and performance to implement intellectual property (IF) blocks and other complex systems consisting of data paths, control logic, I/O, and memories. System-on-chip designers who target FPGAs are increasingly turning towards reusable IP libraries as a means of coping with increased design complexity. Unfortunately, creating libraries of parametric IP for FPGAs is an arduous task. Despite improvements in algorithmic mapping, placement, and routing, high-performance FPGA circuits often require hand-crafted layout. The design problem is further complicated by the requirement that hand-crafted IP target multiple FPGA families. We have developed a method of floorplan specification and evaluation that greatly simplifies the design of such hand-crafted parametric IP. Template-based placement directives are used to specify layout in abstract coordinates that are independent of the sizes of placed components. They provide powerful abstractions for specifying complex geometric relations, and are particularly well-suited to structured circuits that require custom floorplanning to achieve high performance or density. It should be emphasized that for such circuits, all current algorithmic approaches are inadequate. Placement directives relieve the designer of unnecessary tedium by automating the translation from an abstract geometric specification into low-level device coordinates. Although this approach to automation is not new, it is perhaps underappreciated. Superior descriptive abstraction provides substantial benefit in the creation, maintenance, and reuse of hand-crafted parametric IP.