Multiple Precision Floating-Point Arithmetic on SIMD Processors

Current general purpose libraries for multiple precision floating-point arithmetic such as MPFR suffer from a large performance penalty with respect to hard-wired instructions. The performance gap tends to become even larger with the advent of wider SIMD arithmetic in both CPUs and GPUs. In this paper, we present efficient algorithms for multiple precision floating- point arithmetic that are suitable for implementations on SIMD processors. A.C.M. subject classification: G.1.0 Computer-arithmetic A.M.S. subject classification: 65Y04, 65T50, 68W30.