An Energy Efficient VLSI Architecture of Decision Feedback Equalizer for 5G Communication System

Decision feedback equalizer (DFE) is widely used to mitigate the inter-symbol interference. In gigabit applications, the complexity of time domain DFE grows exponentially with feedback filter (FBF) order. In this paper, we have derived low complexity, high throughput architectural designs for time domain DFEs, which meets the requirements of 5G communication systems. These designs are based on the concept of prespeedup the conventional DFE architecture. The number of FBF coefficient combinations to be stored in the lookup table (LUT) and the hardware complexity of proposed designs are reduced by almost (M/2)
^-1
with M being the number of levels in quadrature-amplitude modulation (QAM). The proposed design achieves the throughput nearly 2.15 Gb/s for 16-QAM. A new strategy for updating the FBF coefficients is proposed to improve the convergence rate and steady state error performances without extra hardware overhead. This is based on storing the past decisions in separate LUT, whose contents are updated time to time using parallel error multiplexor. In addition, the bit-errorrate performance of proposed designs is evaluated for different speedup factors in AWGN and Rayleigh fading channels. From the implementation results, it is found that the area, power, and logic utilization of the proposed designs are significantly reduced. For example, an 8th-order FBF of proposed adaptive DFE for 16-QAM occupies times 1.19 less area, 1.04 times less area-time product, with nearly consumes 2.48 times less power and; utilizes 1.93 times less slice LUTs and 2.04 times less flipflops as compared with the best existing scheme.