Reducing dv/dt of Motor Inverters by Staggered-Edge Switching of Multiple Parallel SiC Half-Bridge Cells

A novel concept for reducing the output voltage dv/dt of PWM inverters (especially for traction motor applications) is proposed which however keeps high semiconductor switching speed resulting in low switching losses. Each phase of the intended converter is formed by a parallel arrangement of half-bridge legs which are PWM operated such that a small time-delay is given between the legs (time staggered switching). The output voltages of the legs subsequently are combined by an interphase transformer/inductor network/device to a total output voltage of staircase-type switching edge behavior which finally leads to a much lower dv/dt at the motor terminals despite high-speed semiconductor switching. The paper describes the basic principle and application variants, the dimensioning and the required current balancing. Finally, measurements taken from a laboratory testing setup are presented.