Design of area efficient and low power reed solomon decoder

This paper proposes an area efficient and low power Reed-Solomon (RS) decoder. The proposed decoder is designed using eight stage arithmetic pipelined architecture. The pipelined architecture of RS decoder performs the detection of error locator from the input stream and computes the error magnitude polynomial using the Berleykamp Massey's algorithm. The evaluation of error locator and computation of error magnitude polynomial is computationally intensive and it affects the overall speed of decoder and increases the hardware complexity of RS decoders. The proposed architecture reduces the hardware complexity by more than 40% of compared to earlier hardware designs of RS decoder. The proposed design can be employed in RS decoder and used to decode RS codes defined in Galois field. The design can correct up to eight errors. The decoder operates at a speed of 105MHz and has a gate count of 45,592 gates when implemented in 32nm technology node.