Device Array Layout Synthesis With Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC

Mismatches caused by random and systematic variations among identical designed devices usually dominate the performance of analog circuits, where the former can be controlled by increasing area, while the latter should be tackled by careful layout design. Most of existing studies propose analog placement methodologies with the common centroid constraint to mitigate the linear systematic gradient effect. However, nonlinear gradient error compensation should also be addressed for circuits requiring high performance. This paper presents a current source placement algorithm considering quadratic (second order) gradient error for a high-accuracy current-steering digital-to-analog converter to pursue excellent linearity. A new switching scheme and a submatrix swapping technique are proposed to maximize quadratic gradient compensation, and a simulated annealing-based matrix perturbation algorithm is also proposed to directly minimize integral nonlinearity (INL). In addition, to tackle the extremely high complexity of current source interconnections, we model the routing instance as a branch assignment problem and propose an optimal greedy-based algorithm, which is inspired by the well-known left-edge algorithm. The experimental results show an order of magnitude reduction in INL compared to a state-of-the-art nonlinear gradient-aware current source placement approach and better dynamic performance in post-layout simulation.