Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement

Ultra-low-voltage (ULV) satisfies the energy-constraint on-die acceleration of parallel processing in battery-powered Internet-of-Things applications. However, ULV brings serious leakage energy, throughput reduction, and delay variation issues. Parallel bit-serialization remarkably reduces leakage energy and enhances area efficiency; however, extremely reduced critical path aggravates delay variation makes bit-serial operation not feasible to ULV design. In this paper, we propose a balanced-bit-serial adder (BBSA) as a basic unit of parallel-balanced-bit-serialization (PBBS) operation, which leverages timing borrowing to mitigate delay variation. In addition, we propose two latches to improve the effectiveness of timing borrowing and ease the area and power overhead of BBSA. The proposed BBSA is verified in TSMC 40-nm CMOS technology. Compared with the flip-flop-based bit-serial adder, energy consumption of BBSA is saved by 40% and area efficiency is improved by 15% as well. As a practical demonstration, we present a reconfigurable PBBS single instruction multiple data (SIMD) vector processing tile. The post-layout simulation shows that the proposed design has advantage of overall area efficiency and has significant energy saving as compared with the state-of-art ULV SIMD tile.