Satisfiability modulo theory based methodology for floorplanning in VLSI circuits

This paper proposes a Satisfiability Modulo Theory based formulation for flooplanning in VLSI circuits. The proposed approach allows a number of fixed blocks to be placed within a layout region without overlapping of one block over the other and at the same time area of the layout region is minimized. The proposed approach also allows a number of fixed blocks with ability to rotate and flexible blocks (with variable width and height) to be placed within a layout without overlap. Our target in all cases is reduction in area occupied on a chip which is of vital importance in obtaining a good circuit design. Satisfiability Modulo Theory provides a richer modeling language than is possible with pure Boolean SAT formulas.