Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications

This paper presents the design of RESURF based non-conventional LDMOS and its parametric analysis. The work investigates the impact of three primary parameters relating to p-implant, namely implant placement distance, implant doping and implant thickness, on device performance and premature avalanche breakdown. To avoid undesirable implant-drain punch-through, a boundary of limits is proposed near drain. Further, the implant parameters are optimized to maximize the ratio of Breakdown Voltage Vs On-resistance R
on
to enhance the suitability of the device for High Voltage I/O applications in Sub-micron RF-SoC. A breakdown voltage of 21V at a very low R
on
of 2.5kΩ was achieved for a device gate length of 250nm and gate oxide thickness of 5nm.