The influence of device morphology on wafer-level bonding with polymer-coated layer

The tolerance of device morphology in wafer-level bonding through polymer-coated layer was investigated for the application of 3D integration. Several different pillar heights were fabricated on wafers to simulate the case of bonding with real devices on wafers. Overall, the wafer morphology with polymer-coated layer above devices less than 2 μm can achieve excellent bonding quality. Furthermore, undamaged carrier wafers can be obtained after laser-assisted de-bonding technology and post clean treatment. Based on bonding results, this research can provide a practical concept on device morphology for polymer-based temporary wafer-level bonding in 3D integration.