Through-substrate via (TSV) with embedded capacitor as an on-chip energy storage element

This paper is dedicated to modeling, design, fabrication and characterization of TSV with embedded capacitor, which integrates a TSV and a 3D MIM capacitor into the same trench. An effective capacitance density of 35nF/mm
²
has been demonstrated for the embedded capacitor, which closely matches 37nF/mm
²
from analytical prediction. It is found that conventional sputtering technology is inadequate for electrode deposition of high aspect ratio embedded capacitor, despite its lower cost compared to ALD. Significant enhancement in capacitance density can be expected in embedded capacitor compared to its stand-alone trench capacitor counterpart. A value of 1103nF/mm
²
is envisioned vs. that of 440nF/mm
²
in state-of-the-art multi-layer MIM trench capacitor.